1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising highly capacitive gate structures on the basis of a high-k gate dielectric material of increased permittivity and a work function metal.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold of the completed transistor structures. For instance, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. Moreover, a shift of the work function may be observed when forming appropriate work function metals in an early manufacturing stage, which is believed to be caused by a moderately high oxygen affinity of the metal species, in particular during high temperature processes which may typically be required for completing the transistor structures, for instance for forming drain and source regions and the like.
For this reason, in some approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure. In a corresponding replacement gate approach, the high-k dielectric material may be formed and may be covered by an appropriate metal-containing material, such as titanium nitride and the like, followed by a standard polysilicon or amorphous silicon material, which may then be patterned on the basis of well-established advanced lithography and etch techniques. Consequently, during the process sequence for patterning the gate electrode structure, the sensitive high-k dielectric material may be protected by the metal-containing material, possibly in combination with sophisticated sidewall spacer structures, thereby substantially avoiding any undue material modification during the further processing. After patterning the gate electrode structure, conventional and well-established process techniques for forming the drain and source regions having the desired complex dopant profile are typically performed. After any high temperature processes, the further processing may be continued, for instance, by forming a metal silicide, if required, followed by the deposition of an interlayer dielectric material, such as silicon nitride in combination with silicon dioxide and the like. In this manufacturing stage, a top surface of the gate electrode structures embedded in the interlayer dielectric material may be exposed, for instance, by etch techniques, chemical mechanical polishing (CMP) and the like. In many cases, the polysilicon material may be removed in both types of gate electrode structure in a common etch process and thereafter an appropriate masking regime may be applied in order to selectively fill in an appropriate metal, which may be accomplished by filling in the first metal species and selectively removing the metal species from one of the gate electrode structures. Thereafter, a further metal material may be deposited, thereby obtaining the desired work function for each type of transistor.
Although in general this approach may provide advantages in view of reducing process related non-uniformities in the threshold voltages of the transistors since the high-k dielectric material may be reliably encapsulated during the entire process sequence without requiring an adjustment of the work function and thus the threshold voltage at an early manufacturing stage, the complex process sequence for removing the placeholder material and providing appropriate work function materials for the different types of transistors may also result in a significant degree of variability of the transistor characteristics, which may thus result in offsetting at least some of the advantages obtained by the common processing of the gate electrode structures until the basic transistor configuration is completed. With reference to FIGS. 1a-1c, a typical conventional process strategy will be described in order to illustrate in more detail any problems related to the provision of work function materials for P-channel transistors and N-channel transistors on the basis of a replacement gate approach.
FIG. 1a schematically illustrates a cross-sectional view of a sophisticated semiconductor device 100 in an advanced manufacturing stage, i.e., in a manufacturing stage in which a first transistor 150A, such as a P-channel transistor, and a second transistor 150B, such as an N-channel transistor, are formed in and above corresponding active regions 103A, 103B. The active regions 103A, 103B are laterally delineated by an isolation structure 103C, which is typically comprised of appropriate dielectric materials, such as silicon dioxide, silicon nitride and the like. Moreover, in the advanced manufacturing stage illustrated in FIG. 1a, drain and source regions 153 are provided, possibly in combination with metal silicide regions 154 in order to enhance overall conductivity when forming contact elements that connect to the drain and source regions 153 in a later manufacturing stage. The drain and source regions 153 laterally enclose a channel region 152, the threshold voltage of which may have to be adjusted on the basis of the drain and source regions 153, the general conductivity of the channel region 152 and on the basis of an appropriate gate electrode structure. In the manufacturing stage shown, the transistors 150A, 150B comprise respective gate electrode structures 160A, 160B. The gate electrode structures 160A, 160B may comprise a gate insulation layer 161 that comprises a high-k dielectric material, for instance in the form of hafnium oxide, hafnium silicon oxide and the like. Furthermore, additional “conventional” dielectric materials, such as silicon dioxide-based materials, may be incorporated into the gate insulation layer 161, for instance in view of providing a superior interface with the channel region 152. A titanium nitride cap layer 162 is formed on the gate insulation layer 161, followed by a silicon dioxide-based liner material 163, which may have formed on the cap material 162 in an early manufacturing stage. Furthermore, a tantalum nitride layer 164 in combination with a titanium nitride layer 165 are formed in the gate electrode structures 160A, 160B, wherein, in the example shown in FIG. 1a, the titanium nitride material 165 may represent a work function adjusting material for the transistor 150A, which has to be removed from the gate electrode structure 160B so as to provide therein a further work function adjusting material that is appropriate for the transistor 150B. As is further illustrated in FIG. 1a, the gate electrode structures 160A, 160B may be laterally embedded in a dielectric material, such as a spacer structure 155 and a portion of an interlayer dielectric material 110, which is provided in the form of a silicon nitride-based material 111 and a silicon dioxide material 112.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategy. After forming the active regions 103A, 103B by providing the isolation structure 103C based on well-established process techniques, a gate material stack may be formed, for instance, by providing a conventional gate dielectric base layer, such as a silicon dioxide-based material, followed by a high-k dielectric material, which may be covered by the titanium nitride layer 162. Thereafter, a placeholder material, such as a silicon material, for instance in the form of an amorphous silicon material or a polysilicon material, is deposited, possibly in combination with further materials, such as cap layers and the like, as may typically be required for patterning the gate layer stack and for the further processing of the device 100. During the deposition of the placeholder material, i.e., the silicon material, typically the cap layer 162 may be exposed to an oxygen-containing ambient, which may result in an incorporation of an oxygen species, which is typically converted into a silicon and oxygen-containing material upon depositing the silicon material, thereby forming the liner 163. Next, advanced lithography and patterning strategies may be applied in order to form replacement gate electrode structures having a desired gate length, wherein the sensitive gate insulation layer 161 may be protected by the cap layer 162. Thereafter, the integrity of the sensitive materials 161 and 162 may be increased by providing a sidewall liner 166, for instance by forming a silicon nitride material. Thereafter, the further processing may be continued by forming the drain and source regions 153 in combination with the spacer structure 155, which may be accomplished by any appropriate manufacturing strategy. Thereafter, the metal silicide regions 154 may be formed by well-established process techniques followed by the deposition of the interlayer material 110, for instance in the form of materials 111 and 112. Next, the top surface of the gate electrode structures 160A, 160B may be exposed by removing material of the layer 110, for instance by CMP followed by a selective etch process, for instance based on wet chemical etch recipes and the like, in order to remove the placeholder material, i.e., the silicon material selectively to the spacer structure 155 and the interlayer dielectric material 110. For example, the plurality of efficient wet chemical etch recipes are available, such as potassium hydroxide-based agents, TMAH (tetramethyl ammonium hydroxide) and the like. The etch process may be stopped on the cap layer 162 or, if still present, on the liner 163, depending on the overall process strategy. Thereafter, the tantalum nitride layer 164 is deposited, for instance, by sputter deposition and the like, followed by the deposition of the titanium nitride material 165, which represents the actual work function material for the transistor 150A. The tantalum nitride layer 164 with a thickness of typically less than 5 nm is provided so as to act as an etch stop material for removing the material 165 selectively from the gate electrode structure 160B. For this purpose, an appropriate etch mask 104 is provided, for instance in the form of a resist material and the like, in order to expose the transistor 150B.
FIG. 1b schematically illustrates the semiconductor device 100 when exposed to an etch process 105 for removing the titanium nitride layer 165 (FIG. 1a) selectively to the etch stop layer 164. For convenience, only the transistor 150B is illustrated in FIG. 1b. 
As previously explained, the adjustment of the final work function critically depends on the material species positioned close to the channel region 152, i.e., the gate insulation layer 161 and the titanium nitride cap material 162, possibly in combination with the liner 163, if still present. Furthermore, although titanium nitride may represent a material that may be appropriate for obtaining a desired work function for the transistor 150A, the transistor 150B may require a different atomic species, such as aluminum, lanthanum and the like, in order to obtain the desired high value for the work function, which finally results in the desired threshold voltage of the transistor 150B. Consequently, the tantalum nitride material 164 may be considered disadvantageous in appropriately positioning the work function adjusting material for the transistor 150B in close proximity to the channel region 152 with a high degree of reliability and process uniformity. That is, the tantalum nitride material 164 may generally suppress the diffusion of the desired species such as lanthanum and may have also experienced the etch process 105, thereby resulting in a more or less pronounced degree of modification, which may thus also result in a certain degree of variability during the further processing in adjusting the threshold voltage of the transistor 150B. For this reason, it is highly desirable to remove the tantalum nitride material 164 prior to depositing the work function adjusting material for the transistor 150B.
FIG. 1c schematically illustrates the semiconductor device 100 in a manufacturing stage in which the transistor 150B may be exposed to a sputter etch ambient 106 in order to remove a bottom portion of the tantalum nitride material, which may result in the formation of “sidewall” spacers 1645 of the remaining tantalum nitride material. The sputter etch ambient 106 may typically be established prior to a sputter deposition process for depositing the work function material for the transistor 150B, while, in other cases, if this material has to be provided by a different deposition technique, the ambient 106 may be established as a separate process step. As previously indicated, generally, the thickness of the tantalum nitride material is in the range of 5 nm and less so that the removal process 106 may result in a modification of underlying materials, such as the materials 163, 162 and 161. Consequently, in an area 106C, a high probability of modifying or damaging the layer stack of the gate electrode structure 160B may exist, thereby contributing to a pronounced variability of the resulting transistor characteristics. Consequently, although the removal of the tantalum nitride material may be advantageous in view of a subsequent deposition of the work function material, the sputter etch process 106 may introduce additional process non-uniformities, which may offset the advantages obtained by the removal of the tantalum nitride material 164.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.